Magnetic Tunnel Junction Device and Fabrication

ABSTRACT

A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

FIELD

The present disclosure is generally related to magnetic tunnelingjunction (MTJ) devices and fabrication.

DESCRIPTION OF RELATED ART

MTJ elements may be used to create a magnetic random access memory(MRAM). An MTJ element typically includes a pinned layer, a magnetictunnel barrier, and a free layer, where a bit value is represented by amagnetic moment in the free layer. A bit value stored by an MTJ elementis determined by a direction of the magnetic moment of the free layerrelative to a direction of a fixed magnetic moment carried by the pinnedlayer. The magnetization of the pinned layer is fixed while themagnetization of the free layer may be switched.

When a current flows through the MTJ element, the magnetizationdirection of the free layer may be changed when the current densityexceeds a threshold value, i.e., a critical switching current density(J_(c)). According to a spin-torque-transfer model, J_(c) isproportional to an effective damping constant (α_(eff)), a saturationmagnetization (M_(S)), and a thickness (t_(free)) of the free layer,i.e., J_(c)∝α_(eff) (M_(S))²t_(free). Lowering the critical switchingcurrent density enables low power consumption and smaller chip area ofSTT-MRAM technologies, which may be achieved by reducing one or more ofα_(eff), M_(S), and t_(free).

A spin barrier layer interposed between the free layer and a topelectrical contact of the MTJ element may reduce the effective dampingconstant α_(eff) of the free layer. However, spin barrier layers aretypically insulating layers that may include an oxide of materials, anitride of materials, or a half-metallic layer and so typically have ahigh serial resistance. High serial resistance lowers the tunnelingmagnetoresistance (TMR) of the MTJ device, causing problems for theSTT-MRAM read and write processes. High serial resistance may also limitthe write driving current supply capability of the bitcell.

SUMMARY

A spin torque enhancing layer adjacent to a free layer of an MTJ devicemay include a nano-oxide layer. With the spin torque enhancing layerinserted between the free layer and the top metal contact of the MTJdevice, the spin torque enhancing layer interfaces with the free layer,decreasing the effective damping constant α_(eff) of the free layer.Decreasing the effective damping constant α_(eff) of the free layerdecreases the critical switching current density J_(c) becauseJ_(c)∝α_(eff)(M_(S))²t_(free). Current confined paths extending throughthe nano-oxide layer keep the MTJ serial resistance from increasingsubstantially, so the tunneling magnetoresistance (TMR) of the MTJdevice does not substantially decrease.

In a particular embodiment, an apparatus is disclosed that includes anMTJ device. The MTJ device includes a free layer and a spin torqueenhancing layer responsive to the free layer, the spin torque enhancinglayer including a nano-oxide layer.

In another particular embodiment, an apparatus is disclosed thatincludes an MTJ device. The MTJ device includes a free layer, a tunnelbarrier layer adjacent to the free layer, and a spin torque enhancinglayer adjacent to the free layer. The spin torque enhancing layerincludes a nano-oxide layer. The spin torque enhancing layer is betweenthe free layer and an electrical contact of the MTJ device.

In another particular embodiment, an apparatus is disclosed thatincludes an MTJ device including means for storing a data value as anorientation of a magnetic moment that is programmable by a spinpolarized current exceeding a threshold current density. The MTJ devicealso includes tunneling barrier means for providing conduction electronsto the means for storing by quantum mechanical tunneling of conductionelectrons through a barrier. The MTJ device further includes spin torqueenhancing means for reducing a critical switching current densitythreshold without substantially decreasing a tunneling magnetoresistance(TMR) of the magnetic tunnel junction device. The spin torque enhancingmeans includes a nano-oxide layer, and the means for storing ispositioned between the tunneling barrier means and the spin torqueenhancing means.

In another particular embodiment, a method is disclosed that includesforming a free layer above a tunnel barrier layer of a magnetictunneling junction (MTJ) structure. The method includes forming a spintorque enhancing layer above the free layer. The spin torque enhancinglayer includes a nano-oxide layer.

One particular advantage provided by at least one of the disclosedembodiments is to reduce a critical switching current densityJ_(c)∝α_(eff)(M_(S))²t_(free) by reducing an effective damping constantα_(eff) of a free layer as compared to MTJ devices that do not include aspin torque enhancing layer including a nano-oxide layer. Anotherparticular advantage provided by at least one of the disclosedembodiments is an MTJ structure that does not increase an MTJ serialresistance and does not decrease a tunneling magnetoresistance (TMR) ofthe MTJ device as compared to MTJ devices that do not use a spin torqueenhancing layer including a nano-oxide layer. Other aspects, advantages,and features of the present disclosure will become apparent after reviewof the entire application, including the following sections: BriefDescription of the Drawings, Detailed Description, and the Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a first illustrative embodiment of a magnetic tunnelingjunction (MTJ) device with a spin torque enhancing layer including anano-oxide layer;

FIG. 2 is a second illustrative embodiment of a magnetic tunnelingjunction (MTJ) device with a spin torque enhancing layer including anano-oxide layer;

FIG. 3 is an illustrative embodiment of an element of aspin-torque-transfer magnetic random access memory (STT-MRAM) includinga magnetic tunneling junction (MTJ) device with a spin torque enhancinglayer that includes a nano-oxide layer;

FIG. 4 is an illustrative embodiment of a memory array including amagnetic tunneling junction (MTJ) structure with a spin torque enhancinglayer including a nano-oxide layer;

FIG. 5 is a flow diagram of an illustrative embodiment of a method offorming a magnetic tunneling junction (MTJ) device;

FIG. 6 is a block diagram of a particular embodiment of a portablecommunication device including a module having MTJ structures thatinclude a spin torque enhancing layer including a nano-oxide layer; and

FIG. 7 is a data flow diagram illustrating a manufacturing process foruse with magnetic tunneling junction (MTJ) devices having a spin torqueenhancing layer as described in FIGS. 1-6.

DETAILED DESCRIPTION

Referring to FIG. 1, a first illustrative embodiment of a magnetictunneling junction (MTJ) device with a spin torque enhancing layerincluding a nano-oxide layer is depicted and generally designated 100.The MTJ device 100 includes a bottom contact 102, an anti-ferromagnetic(AF) pinning layer 104, a pinned layer 112, a tunnel barrier layer 114,a free layer 116, a spin torque enhancing layer including a nano-oxidelayer 118, and a top contact 120. In a particular embodiment, the pinnedlayer 112 is a composite layer and includes a CoFe ferromagnetic layer106, an Ru non-magnetic layer 108, and a CoFeB ferromagnetic layer 110.

The spin torque enhancing layer including the nano-oxide layer 118 mayinclude one or more conductive islands 122 of conductive materialextending therethrough connecting the free layer 116 and the top contact120. The spin torque enhancing layer including the nano-oxide layer 118may also have one or more conductive paths 124 of conductive materialextending therethrough also connecting the free layer 116 and the topcontact 120. The one or more conductive islands 122 and the one or moreconductive paths 124 may be surrounded by insulating material 126.

In a particular embodiment, the spin torque enhancing layer includingthe nano-oxide layer 118 reduces a critical switching current densitythreshold without substantially decreasing a tunneling magnetoresistance(TMR) of the MTJ device 100. In a particular embodiment, the tunnelingmagnetoresistance (TMR) is a ratio of a difference between a firstresistance (R₁) in a first state of the MTJ device 100 and a secondresistance (R₀) in a second state of the MTJ device 100 to the secondresistance (R₀) in the second state of the MTJ device 100. For example,

${T\; M\; R} = {\frac{R_{1} - R_{0}}{R_{0}}.}$

In a particular embodiment, the spin torque enhancing layer includingthe nano-oxide layer 118 reduces a critical switching current densitythreshold without substantially increasing a resistance of the MTJdevice 100. The spin torque enhancing layer including the nano-oxidelayer 118 may be responsive to the free layer 116 by reducing theeffective damping constant α_(eff) of the free layer 116, to reduce thecritical switching current density threshold J_(c) becauseJ_(c)∝ζ_(eff)(M_(S))²t_(free).

In a particular embodiment, the spin torque enhancing layer includingthe nano-oxide layer 118 includes an oxidation layer of a non-magneticmetal alloy. For example, the spin torque enhancing layer including thenano-oxide layer 118 may be formed by oxidizing a non-magnetic alloy.For example, a non-magnetic metal aluminum copper Al₉₀Cu₁₀ alloy may bedeposited on the free layer 116 and oxidized to form an aluminum oxideAl₂O₃ insulating material 126, with the unoxidized metal of the Al₉₀Cu₁₀forming the one or more conductive islands 122 and the one or moreconductive paths 124. The thickness of the non-magnetic metal aluminumcopper Al₉₀Cu₁₀ alloy may be changed to control the number and thedensity of the one or more conductive islands 122 and the one or moreconductive paths 124.

The insulating material 126 may include an oxide of materials from agroup consisting of Mg, Al, B, Si, Ge, W, Nb, Mo, Ta, V, Ti, Cr, Fe, Co,Ni, and Cu. The insulating material 126 may also include a nitride ofmaterials from a group consisting of Al, B, Si, Ge, Ti, and Pt. Theinsulating material 126 may also include at least one material from thegroup consisting of Si, Ge, Ga, Cd, Te, Sb, In, Al, As, Hg, C, and Cr.The insulating material 126 may also include half-metallic materials,such as Sr₂FeMoO₆, (La_(0.7)Sr_(0.3))MnO₃, NiMnSb, Fe₃O₄, and CrO₂. Theone or more conductive islands 122 and the one or more conductive paths124 may include one or more materials from a group consisting of Cu, Ag,Au, Pt, Pd, Ir, Os, Cr, Ta, Mg, Ti, Si, Al, Ni, Fe, and Co.

Referring to FIG. 2, a second illustrative embodiment of a magnetictunneling junction (MTJ) device with a spin torque enhancing layerincluding a nano-oxide layer is depicted and generally designated 200.The MTJ device 200 may be similar to the MTJ device 100 of FIG. 1. TheMTJ device 200 includes a bottom contact 202, an anti-ferromagnetic (AF)pinning layer 204, a pinned layer 212, a tunnel barrier layer 214, afree layer 216, a spin torque enhancing layer including a nano-oxidelayer 218, a capping layer 222, and a top contact 220. In a particularembodiment, the pinned layer 212 is a composite layer and includes aCoFe ferromagnetic layer 206, an Ru non-magnetic layer 208, and a CoFeBferromagnetic layer 210. In a particular embodiment, the free layer 216is a composite layer and includes a first ferromagnetic layer 228, suchas CoFeB, and a second ferromagnetic layer 230, such as NiFe.

The spin torque enhancing layer including the nano-oxide layer 218 maybe similar to the spin torque enhancing layer including the nano-oxidelayer 118 of FIG. 1. The spin torque enhancing layer including thenano-oxide layer 218 may have one or more conductive islands ofconductive material, similar to the one or more conductive islands 122of FIG. 1, extending therethrough connecting the free layer 216 and thecapping layer 222. The spin torque enhancing layer including thenano-oxide layer 218 may also have one or more conductive paths 224 ofconductive material extending therethrough also connecting the freelayer 216 and the capping layer 222. The one or more conductive islandsand the one or more conductive paths 224 may be surrounded by insulatingmaterial 226.

In a particular embodiment, the spin torque enhancing layer includingthe nano-oxide layer 218 reduces a critical switching current densitythreshold without substantially decreasing a tunneling magnetoresistance(TMR) of the MTJ device 200. In a particular embodiment, the spin torqueenhancing layer including the nano-oxide layer 218 reduces a criticalswitching current density threshold without substantially increasing aresistance of the MTJ device 200.

Referring to FIG. 3, a first illustrative embodiment of an element of aspin-torque-transfer magnetic random access memory (STT-MRAM) isdepicted and generally designated 300. The element of the STT-MRAM 300includes a memory cell having a magnetic tunneling junction (MTJ) device301 and an access transistor 316 on a substrate 326. The MTJ device 301includes an access transistor electrode 314, a seed layer 303, ananti-ferromagnetic (AF) pinning layer 304, a pinned layer 306, a tunnelbarrier layer 308, a free layer 312, a nano-oxide layer 392, and a bitline access electrode 302 coupled to a bit line 318. In a particularembodiment, the free layer 312 is a composite layer that includes afirst ferromagnetic portion 310 and a second ferromagnetic portion 390.The access transistor electrode 314 is coupled to a drain region 330 ofthe access transistor 316. The access transistor 316 is gated by a wordline 319 and has a source region 332 coupled to a source contact 320.

The seed layer 303 is in contact with the access transistor electrode314. The seed layer 303 provides a surface for MTJ film deposition andcan be composed of several different layers. The AF pinning layer 304 isin contact with the seed layer 303. The AF pinning layer 304 causes anorientation of a magnetic moment 325 of the pinned layer 306 to bepinned in a particular direction. The pinned layer 306 is in contactwith the AF pinning layer 304 and may be composed of a ferromagneticmaterial.

The tunnel barrier layer 308 is in contact with the pinned layer 306 andphysically isolates the pinned layer 306 from the free layer 312 whileenabling current flow via electrons quantum mechanically tunnelingacross the tunnel barrier layer 308. The tunnel barrier layer 308 may becomposed of a non-magnetic material. In an illustrative embodiment, thetunnel barrier layer 308 includes magnesium oxide (MgO).

The free layer 312 is in contact with the tunnel barrier layer 308 andis located at a distance d1 340 from the substrate 326. The free layer312 has a magnetic moment 324 that may be in a parallel or antiparallelalignment with the magnetic moment 325 of the pinned layer 306. Thepinned layer 306 may be at a distance d2 342 from the substrate 326where the distance d2 342 is less than the distance d1 340. The freelayer 312 is above the pinned layer 306 relative to the substrate 326.The magnetic moment 324 of the free layer 312 may be written by acurrent exceeding a critical switching current and may be read using acurrent that is less than the critical switching current. For example,the read current may be much less than the critical switching current toprevent read disturbances. In an illustrative embodiment, the free layer312 is a single ferromagnetic layer. In another illustrative embodiment,the free layer 312 is a composite layer of two ferromagnetic layers. Ina particular embodiment, the two ferromagnetic layers may sandwich anon-magnetic spacer (not shown). In another illustrative embodiment, thefree layer 312 is a synthetic ferromagnetic layer or a syntheticantiferromagnetic layer.

In a particular embodiment, the free layer 312 is a composite layer thatincludes the first ferromagnetic portion 310 and the secondferromagnetic portion 390. In a particular embodiment, the firstferromagnetic portion 310 includes cobalt and iron. For example, thefirst ferromagnetic portion 310 may include CoFe, CoFe—X (such asCoFeB), CoFe—X—Y, or any combination thereof In a particular embodiment,the second ferromagnetic portion 390 includes nickel and iron. Forexample, the second ferromagnetic portion 390 may include NiFe,permalloy, or any combination thereof.

The nano-oxide layer 392 is in contact with the free layer 312. In aparticular embodiment, the nano-oxide layer 392 includes an oxidationlayer of a non-magnetic metal alloy. For example, the non-magnetic metalalloy aluminum copper Al₉₀Cu₁₀ may be deposited on the free layer 312and oxidized to form the nano-oxide layer 392. The nano-oxide layer 392may be configured to decrease the critical switching current densityJ_(c)∝α_(eff)(M_(S))²t_(free), by decreasing the effective dampingconstant α_(eff) of the free layer 312, without substantially increasingthe resistance of the MTJ device 301.

Because the resistance of the MTJ device 301 does not substantiallyincrease, the tunneling magnetoresistance (TMR) of the MTJ device 301does not substantially decrease. For example, using

${{T\; M\; R} = \frac{R_{1} - R_{0}}{R_{0}}},$

an increase in the resistance ΔR of the MTJ device 301 would cause theTMR of the MTJ device 301 to decrease because

${T\; M\; R_{\Delta \; R}} = {\frac{\left( {R_{1} + {\Delta \; R}} \right) - \left( {R_{0} + {\Delta \; R}} \right)}{\left( {R_{0} + {\Delta \; R}} \right)} = {{\frac{R_{1} - R_{0}}{R_{0} + {\Delta \; R}} < \frac{R_{1} - R_{0}}{R_{0}}} = {T\; M\; {R.}}}}$

The nano-oxide layer 392 decreases the critical switching currentdensity J_(c)∝α_(eff)(M_(S))²t_(free) without substantially decreasingthe TMR of the MTJ device 301. Smaller critical switching currentdensity J_(c) can enable smaller devices, higher density memory arrays,lower power operation, higher clocking frequency, or any combinationthereof.

The direction in which a write current is passed through the MTJ device301 determines whether the magnetic moment 324 of the free layer 312 isaligned to be parallel or anti-parallel to the magnetic moment 325 ofthe pinned layer 306. In an illustrative embodiment, a data “1” valuemay be stored by passing a first write current from the bit line accesselectrode 302 to the access transistor electrode 314 to align themagnetic moment 324 anti-parallel to the magnetic moment 325. A data “0”value may be stored by passing a second write current from the accesstransistor electrode 314 to the bit line access electrode 302 to alignthe magnetic moment 324 parallel to the magnetic moment 325.

When a read operation 322 is performed at the STT-MRAM 300, a readcurrent may flow from the bit line access electrode 302 to the source320 or the read current may flow from the source 320 to the bit lineaccess electrode 302. In a particular embodiment, a direction of theread current may be determined based on which direction provides thelargest read signal. In a particular embodiment, when the read operation322 is performed on the element of the STT-MRAM 300, a read currentflows through the bit line (BL) 318, in a direction from the bitlineaccess electrode 302 to the access transistor electrode 314. The readcurrent through the MTJ device 301 encounters a resistance correspondingto a relative orientation of the magnetic moment 325 and the magneticmoment 324. When the magnetic moment 325 of the pinned layer 306 has aparallel orientation to the magnetic moment 324 of the free layer 312,the read current encounters a resistance different than when themagnetic moment 325 of the pinned layer 306 has an anti-parallelorientation to the magnetic moment 324 of the free layer 312. Generally,when the magnetic moment 325 of the pinned layer 306 has a parallelorientation to the magnetic moment 324 of the free layer 312, the readcurrent encounters a lower resistance than when the magnetic moment 325of the pinned layer 306 has an anti-parallel orientation to the magneticmoment 324 of the free layer 312.

The bitcell may therefore be used as an element of a memory device, suchas an STT-MRAM 300. By employing an appropriate nano-oxide layer 392,the effective damping constant α_(eff) of the free layer 312 may besubstantially reduced, decreasing a critical switching current densityJ_(c)∝α_(eff)(M_(S))²t_(free). Employing the nano-oxide layer 392 maydecrease the critical switching current densityJ_(c)∝α_(eff)(M_(S))²t_(free) without substantially increasing theresistance of the MTJ device 301. Because the resistance of the MTJdevice 301 does not substantially increase, the tunnelingmagnetoresistance (TMR) of the MTJ device 301 does not substantiallydecrease. Lower power operation and less heat generation may result fromdecreasing the critical switching current density J_(c) withoutsubstantially decreasing the tunneling magnetoresistance (TMR) of theMTJ device 301, and operation using shorter write pulse lengths andhigher clock frequency may also be enabled.

Referring to FIG. 4, an illustrative embodiment of a memory system isdepicted and generally designated 400. The memory system 400 includes amemory array 480, such as an STT-MRAM memory array, that includesmultiple memory cells, including a representative memory cell 482 and arepresentative pair of reference cells that store a logical high valueR₁ 470 and a logical low value R₀ 472. A sense amplifier 484 is coupledto receive an output from a selected memory cell in addition toreceiving outputs from the reference cells. The sense amplifier 484 isconfigured to produce an amplifier output 486 that indicates a valuestored at the selected memory cell.

The memory cell 482 includes an MTJ structure 401 coupled to an accesstransistor 428. The MTJ structure 401 includes a top contact 402, anano-oxide layer 492, a free layer 412 having a magnetic moment 424, atunnel barrier layer 408, a pinned layer 406 having a pinned magneticmoment 425, an anti-ferromagnetic (AF) pinning layer 404, a seed layer403, and a bottom contact 418. The access transistor 428 is coupled tothe bottom contact 418 and coupled to a word line 430 and a source line432.

The top contact 402 provides a first electrical contact to a bit line422. The AF pinning layer 404 fixes an orientation of the magneticmoment 425 of the pinned layer 406. The pinned layer 406 may be asynthetic antiferromagnetic pinned layer including multiple layers, andmay be similar to the pinned layer 112 of FIG. 1 or the pinned layer 212of FIG. 2. The tunnel barrier layer 408 may restrict free electronaccess but enables a tunneling current to the free layer 412. The freelayer 412 may store a data value as an orientation of the magneticmoment 424 that is programmable by application of a spin polarizedcurrent that exceeds a critical switching current. The free layer 412 ispositioned between the tunnel barrier layer 408 and the nano-oxide layer492. The nano-oxide layer 492 is positioned between the free layer 412and the top contact 402 of the MTJ structure 401.

In a particular embodiment, the free layer 412 is a composite layer thatincludes a first ferromagnetic portion 410 and a second ferromagneticportion 490. In a particular embodiment, the first ferromagnetic portion410 includes cobalt and iron. For example, the first ferromagneticportion 410 may include CoFe, CoFe—X (such as CoFeB), CoFe—X—Y, or anycombination thereof In a particular embodiment, the second ferromagneticportion 490 includes nickel and iron. For example, the secondferromagnetic portion 490 may include NiFe, permalloy, or anycombination thereof

The nano-oxide layer 492 may decrease the critical switching currentdensity J_(c) of the MTJ structure 401 without substantially decreasingthe tunneling magnetoresistance (TMR) of the MTJ structure 401 in amanner substantially similar to the nano-oxide layer 392 of FIG. 3. Thenano-oxide layer 492 may decrease the critical switching current densityJ_(c)∝α_(eff)(M_(S))²t_(free) without substantially increasing aresistance of the MTJ structure 401 in a manner substantially similar tothe nano-oxide layer 392 of FIG. 3.

The memory array 480 depicted in FIG. 4 may include multiple cellssubstantially similar to the representative memory cell 482. The memoryarray 480, or any other array of cells using the MTJ device 100 of FIG.1, the MTJ device 200 of FIG. 2, the MTJ device 301 of FIG. 3, or theMTJ structure 401 of FIG. 4, may be implemented in an embedded memory,such as a level two (L2) cache or another type of embedded memory, as anillustrative example. Such an array of MTJ cells may be implemented as aSTT-MRAM memory to replace memory arrays that use static random accessmemory (SRAM), dynamic random access memory (DRAM) or flash memorytechnologies, for example.

FIG. 5 is a flow diagram of an illustrative embodiment 500 of a methodof forming a magnetic tunneling junction (MTJ) device. In theillustrative embodiment 500, the MTJ device may be the MTJ device 100 ofFIG. 1, the MTJ device 200 of FIG. 2, the MTJ device 301 of FIG. 3, orthe MTJ structure 401 of FIG. 4. In the illustrative embodiment 500, themethod includes forming a magnetic tunneling junction by forming ananti-ferromagnetic (AF) pinning layer above a bottom contact, at 502,forming a pinned layer above the anti-ferromagnetic (AF) pinning layer,at 504, forming a tunnel barrier layer above the pinned layer, at 506,and forming a free layer above the tunnel barrier layer, at 508.

Moving to 510, a spin torque enhancing layer is formed above the freelayer, the spin torque enhancing layer including a nano-oxide layer. Forexample, the spin torque enhancing layer including the nano-oxide layer118 of FIG. 1 may be formed above the free layer 116 of FIG. 1.Similarly, the spin torque enhancing layer including the nano-oxidelayer 218 of FIG. 2 may be formed above the free layer 216 of FIG. 2.Likewise, the nano-oxide layer 392 of FIG. 3 may be formed above thefree layer 312 of FIG. 3. Similarly, the nano-oxide layer 492 of FIG. 4may be formed above the free layer 412 of FIG. 4.

Continuing to 512, the nano-oxide layer may be formed by oxidizing anon-magnetic metal alloy. For example, a non-magnetic metal alloyaluminum copper Al₉₀Cu₁₀ may be deposited on the free layer 116 of FIG.1 and oxidized to form an aluminum oxide Al₂O₃ insulating material 126of FIG. 1, with the unoxidized metal of the alloy forming the one ormore conductive islands 122 of FIG. 1 and the one or more conductivepaths 124 of FIG. 1. For another example, a non-magnetic metal Mg may bedeposited on the free layer 116 of FIG. 1 and partially oxidized to forma magnesium oxide MgO insulating material 126 of FIG. 1, with theunoxidized metal of Mg forming the one or more conductive islands 122 ofFIG. 1 and the one or more conductive paths 124 of FIG. 1.

The depositing and forming of the materials and the layers may becontrolled by a processor integrated into an electronic device. Forexample, the electronic device may be a computer configured to controlfabrication machinery.

In other embodiments, the method of FIG. 5 may be performed in an orderthat is different than depicted. For example, the spin torque enhancinglayer including the nano-oxide layer may be formed prior to formation ofthe free layer. In an alternative embodiment, the MTJ device that isformed may have a reversed structure than depicted in FIG. 3, with thenano-oxide layer closer to the substrate than the free layer and withthe free layer closer to the bit line than the nano-oxide layer.

FIG. 6 is a block diagram of particular embodiment of a system 600including a module having MTJ structures that each include a nano-oxidelayer 664. The system 600 may be implemented in a portable electronicdevice and includes a processor 610, such as a digital signal processor(DSP), coupled to computer readable medium, such as a memory 632,storing computer readable instructions, such as software 667. The system600 includes the module having MTJ structures with a nano-oxide layer664. In an illustrative example, the module having MTJ structures 664includes any of the MTJ structures of FIGS. 1-4, produced in accordancewith any of the embodiments of FIG. 5 or FIG. 7, or any combinationthereof. The module having MTJ structures 664 may be in the processor610 or may be a separate device or circuitry (not shown). In aparticular embodiment, as shown in FIG. 6, the module having MTJstructures 664 is accessible to the digital signal processor (DSP) 610.In another particular embodiment, the memory 632 may include an STT-MRAMmemory array that includes the module having MTJ structures 664.

A camera interface 668 is coupled to the processor 610 and also coupledto a camera, such as a video camera 670. A display controller 626 iscoupled to the processor 610 and to a display device 628. Acoder/decoder (CODEC) 634 can also be coupled to the processor 610. Aspeaker 636 and a microphone 638 can be coupled to the CODEC 634. Awireless interface 640 can be coupled to the processor 610 and to awireless antenna 642.

In a particular embodiment, the processor 610, the display controller626, the memory 632, the CODEC 634, the wireless interface 640, and thecamera interface 668 are included in a system-in-package orsystem-on-chip device 622. In a particular embodiment, an input device630 and a power supply 644 are coupled to the system-on-chip device 622.Moreover, in a particular embodiment, as illustrated in FIG. 6, thedisplay device 628, the input device 630, the speaker 636, themicrophone 638, the wireless antenna 642, the video camera 670, and thepower supply 644 are external to the system-on-chip device 622. However,each of the display device 628, the input device 630, the speaker 636,the microphone 638, the wireless antenna 642, the video camera 670, andthe power supply 644 can be coupled to a component of the system-on-chipdevice 622, such as an interface or a controller.

The foregoing disclosed devices and functionalities (such as the devicesof FIG. 1, FIG. 2, FIG. 3 or FIG. 4, the method of FIG. 5, or anycombination thereof) may be designed and configured into computer files(e.g., RTL, GDSII, GERBER, etc.) stored on computer readable media. Someor all such files may be provided to fabrication handlers who fabricatedevices based on such files. Resulting products include semiconductorwafers that are then cut into semiconductor die and packaged into asemiconductor chip. The semiconductor chips are then employed inelectronic devices. FIG. 7 depicts a particular illustrative embodimentof an electronic device manufacturing process 700.

Physical device information 702 is received in the manufacturing process700, such as at a research computer 706. The physical device information702 may include design information representing at least one physicalproperty of a semiconductor device, such as the MTJ device 100 of FIG.1, the MTJ device 200 of FIG. 2, the MTJ device 301 of FIG. 3, thememory array 480 of FIG. 4, the memory cell 482 of FIG. 4, the MTJstructure 401 of FIG. 4, or any combination thereof. For example, thephysical device information 702 may include physical parameters,material characteristics, and structure information that is entered viaa user interface 704 coupled to the research computer 706. The researchcomputer 706 includes a processor 708, such as one or more processingcores, coupled to a computer readable medium such as a memory 710. Thememory 710 may store computer readable instructions that are executableto cause the processor 708 to transform the physical device information702 to comply with a file format and to generate a library file 712.

In a particular embodiment, the library file 712 includes at least onedata file including the transformed design information. For example, thelibrary file 712 may include a library of semiconductor devicesincluding the MTJ device 100 of FIG. 1, the MTJ device 200 of FIG. 2,the MTJ device 301 of FIG. 3, the memory array 480 of FIG. 4, the memorycell 482 of FIG. 4, the MTJ structure 401 of FIG. 4, or any combinationthereof, that is provided for use with an electronic design automation(EDA) tool 720.

The library file 712 may be used in conjunction with the EDA tool 720 ata design computer 714 including a processor 716, such as one or moreprocessing cores, coupled to a memory 718. The EDA tool 720 may bestored as processor executable instructions at the memory 718 to enablea user of the design computer 714 to design a circuit using the MTJdevice 100 of FIG. 1, the MTJ device 200 of FIG. 2, the MTJ device 301of FIG. 3, the memory array 480 of FIG. 4, the memory cell 482 of FIG.4, the MTJ structure 401 of FIG. 4, or any combination thereof, of thelibrary file 712. For example, a user of the design computer 714 mayenter circuit design information 722 via a user interface 724 coupled tothe design computer 714. The circuit design information 722 may includedesign information representing at least one physical property of asemiconductor device, such as the MTJ device 100 of FIG. 1, the MTJdevice 200 of FIG. 2, the MTJ device 301 of FIG. 3, the memory array 480of FIG. 4, the memory cell 482 of FIG. 4, the MTJ structure 401 of FIG.4, or any combination thereof. To illustrate, the circuit designproperty may include identification of particular circuits andrelationships to other elements in a circuit design, positioninginformation, feature size information, interconnection information, orother information representing a physical property of a semiconductordevice.

The design computer 714 may be configured to transform the designinformation, including the circuit design information 722, to complywith a file format. To illustrate, the file formation may include adatabase binary file format representing planar geometric shapes, textlabels, and other information about a circuit layout in a hierarchicalformat, such as a Graphic Data System (GDSII) file format. The designcomputer 714 may be configured to generate a data file including thetransformed design information, such as a GDSII file 726 that includesinformation describing the MTJ device 100 of FIG. 1, the MTJ device 200of FIG. 2, the MTJ device 301 of FIG. 3, the memory array 480 of FIG. 4,the memory cell 482 of FIG. 4, the MTJ structure 401 of FIG. 4, or anycombination thereof, in addition to other circuits or information. Toillustrate, the data file may include information corresponding to asystem-on-chip (SOC) that includes the memory array 480 of FIG. 4 andthat also includes additional electronic circuits and components withinthe SOC.

The GDSII file 726 may be received at a fabrication process 728 tomanufacture the MTJ device 100 of FIG. 1, the MTJ device 200 of FIG. 2,the MTJ device 301 of FIG. 3, the memory array 480 of FIG. 4, the memorycell 482 of FIG. 4, the MTJ structure 401 of FIG. 4, or any combinationthereof, according to transformed information in the GDSII file 726. Forexample, a device manufacture process may include providing the GDSIIfile 726 to a mask manufacturer 730 to create one or more masks, such asmasks to be used for photolithography processing, illustrated as arepresentative mask 732. The mask 732 may be used during the fabricationprocess to generate one or more wafers 734, which may be tested andseparated into dies, such as a representative die 736. The die 736includes a circuit including the MTJ device 100 of FIG. 1, the MTJdevice 200 of FIG. 2, the MTJ device 301 of FIG. 3, the memory array 480of FIG. 4, the memory cell 482 of FIG. 4, the MTJ structure 401 of FIG.4, or any combination thereof.

The die 736 may be provided to a packaging process 738 where the die 736is incorporated into a representative package 740. For example, thepackage 740 may include the single die 736 or multiple dies, such as asystem-in-package (SiP) arrangement. The package 740 may be configuredto conform to one or more standards or specifications, such as JointElectron Device Engineering Council (JEDEC) standards.

Information regarding the package 740 may be distributed to variousproduct designers, such as via a component library stored at a computer746. The computer 746 may include a processor 748, such as one or moreprocessing cores, coupled to a memory 750. A printed circuit board (PCB)tool may be stored as processor executable instructions at the memory750 to process PCB design information 742 received from a user of thecomputer 746 via a user interface 744. The PCB design information 742may include physical positioning information of a packaged semiconductordevice on a circuit board, the packaged semiconductor devicecorresponding to the package 740 including the MTJ device 100 of FIG. 1,the MTJ device 200 of FIG. 2, the MTJ device 301 of FIG. 3, the memoryarray 480 of FIG. 4, the memory cell 482 of FIG. 4, the MTJ structure401 of FIG. 4, or any combination thereof.

The computer 746 may be configured to transform the PCB designinformation 742 to generate a data file, such as a GERBER file 752 withdata that includes physical positioning information of a packagedsemiconductor device on a circuit board, as well as layout of electricalconnections such as traces and vias, where the packaged semiconductordevice corresponds to the package 740 including the MTJ device 100 ofFIG. 1, the MTJ device 200 of FIG. 2, the MTJ device 301 of FIG. 3, thememory array 480 of FIG. 4, the memory cell 482 of FIG. 4, the MTJstructure 401 of FIG. 4, or any combination thereof. In otherembodiments, the data file generated by the transformed PCB designinformation may have a format other than a GERBER format.

The GERBER file 752 may be received at a board assembly process 754 andused to create PCBs, such as a representative PCB 756, manufactured inaccordance with the design information stored within the GERBER file752. For example, the GERBER file 752 may be uploaded to one or moremachines for performing various steps of a PCB production process. ThePCB 756 may be populated with electronic components including thepackage 740 to form a representative printed circuit assembly (PCA) 758.

The PCA 758 may be received at a product manufacture process 760 andintegrated into one or more electronic devices, such as a firstrepresentative electronic device 762 and a second representativeelectronic device 764. As an illustrative, non-limiting example, thefirst representative electronic device 762, the second representativeelectronic device 764, or both, may be selected from the group of a settop box, a music player, a video player, an entertainment unit, anavigation device, a communications device, a personal digital assistant(PDA), a fixed location data unit, and a computer. As anotherillustrative, non-limiting example, one or more of the electronicdevices 762 and 764 may be remote units such as mobile phones, hand-heldpersonal communication systems (PCS) units, portable data units such aspersonal data assistants, global positioning system (GPS) enableddevices, navigation devices, fixed location data units such as meterreading equipment, or any other device that stores or retrieves data orcomputer instructions, or any combination thereof. Although FIG. 7illustrates remote units according to the teachings of the disclosure,the disclosure is not limited to these exemplary illustrated units.Embodiments of the disclosure may be suitably employed in any devicewhich includes active integrated circuitry including memory and on-chipcircuitry.

Thus, the MTJ device 100 of FIG. 1, the MTJ device 200 of FIG. 2, theMTJ device 301 of FIG. 3, the memory array 480 of FIG. 4, the memorycell 482 of FIG. 4, the MTJ structure 401 of FIG. 4, or any combinationthereof, may be fabricated, processed, and incorporated into anelectronic device, as described in the illustrative process 700. One ormore aspects of the embodiments disclosed with respect to FIGS. 1-5 maybe included at various processing stages, such as within the libraryfile 712, the GDSII file 726, and the GERBER file 752, as well as storedat the memory 710 of the research computer 706, the memory 718 of thedesign computer 714, the memory 750 of the computer 746, the memory ofone or more other computers or processors (not shown) used at thevarious stages, such as at the board assembly process 754, and alsoincorporated into one or more other physical embodiments such as themask 732, the die 736, the package 740, the PCA 758, other products suchas prototype circuits or devices (not shown), or any combination thereofFor example, the GDSII file 726 or the fabrication process 728 caninclude a computer readable tangible medium storing instructionsexecutable by a computer, the instructions including instructions thatare executable by the computer to initiate formation of a free layerabove a tunnel barrier layer of a magnetic tunneling junction structureand instructions that are executable by the computer to initiateformation of a spin torque enhancing layer above the free layer, thespin torque enhancing layer including a nano-oxide layer. Althoughvarious representative stages of production from a physical devicedesign to a final product are depicted, in other embodiments fewerstages may be used or additional stages may be included. Similarly, theprocess 700 may be performed by a single entity, or by one or moreentities performing various stages of the process 700.

Those of skill would further appreciate that the various illustrativelogical blocks, configurations, modules, circuits, and method stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software executed by aprocessing unit, or combinations of both. Various illustrativecomponents, blocks, configurations, modules, circuits, and steps havebeen described above generally in terms of their functionality. Whethersuch functionality is implemented as hardware or executable processinginstructions depends upon the particular application and designconstraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentdisclosure.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in random access memory (RAM), amagnetoresistive random access memory (MRAM), a spin-torque-transfermagnetoresistive random access memory (STT-MRAM), flash memory,read-only memory (ROM), programmable read-only memory (PROM), erasableprogrammable read-only memory (EPROM), electrically erasableprogrammable read-only memory (EEPROM), registers, hard disk, aremovable disk, a compact disc read-only memory (CD-ROM), or any otherform of storage medium known in the art. An exemplary storage medium iscoupled to the processor such that the processor can read informationfrom, and write information to, the storage medium. In the alternative,the storage medium may be integral to the processor. The processor andthe storage medium may reside in an application-specific integratedcircuit (ASIC). The ASIC may reside in a computing device or a userterminal. In the alternative, the processor and the storage medium mayreside as discrete components in a computing device or user terminal.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the disclosedembodiments. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the principles defined hereinmay be applied to other embodiments without departing from the scope ofthe disclosure. Thus, the present disclosure is not intended to belimited to the embodiments shown herein but is to be accorded the widestscope possible consistent with the principles and novel features asdefined by the following claims.

1. An apparatus comprising: a magnetic tunneling junction devicecomprising: a free layer; and a spin torque enhancing layer responsiveto the free layer, the spin torque enhancing layer comprising anano-oxide layer.
 2. The apparatus of claim 1, wherein the nano-oxidelayer includes an oxidation layer of a non-magnetic metal alloy.
 3. Theapparatus of claim 1, wherein the free layer is a single layer.
 4. Theapparatus of claim 1, wherein the free layer is a composite layer of twoferromagnetic layers.
 5. The apparatus of claim 1, wherein the freelayer is a composite layer of two ferromagnetic layers sandwiching anon-magnetic spacer layer.
 6. The apparatus of claim 1, wherein the freelayer is a synthetic antiferromagnetic layer.
 7. The apparatus of claim1, wherein the free layer is a synthetic ferromagnetic layer.
 8. Theapparatus of claim 1, wherein the spin torque enhancing layer comprisingthe nano-oxide layer further comprises one or more conductive islands ofconductive material extending therethrough and one or more conductivepaths of conductive material extending therethrough, the one or moreconductive islands and the one or more conductive paths surrounded byinsulating material.
 9. The apparatus of claim 1, wherein the spintorque enhancing layer reduces a critical switching current densitythreshold without substantially decreasing a tunneling magnetoresistance(TMR) of the magnetic tunneling junction device.
 10. The apparatus ofclaim 9, wherein the tunneling magnetoresistance (TMR) is a ratio of adifference between a first resistance in a first state of the magnetictunneling junction device and a second resistance in a second state ofthe magnetic tunneling junction device to the second resistance in thesecond state of the magnetic tunneling junction device.
 11. Theapparatus of claim 1, further comprising a tunnel barrier layer adjacentto the free layer.
 12. The apparatus of claim 1, further comprising acapping layer adjacent to the spin torque enhancing layer.
 13. Theapparatus of claim 1, integrated into at least one semiconductor die.14. The apparatus of claim 1, further comprising a memory array thatincludes the magnetic tunneling junction device.
 15. The apparatus ofclaim 14, further comprising a device, selected from the groupconsisting of a set top box, a music player, a video player, anentertainment unit, a navigation device, a communications device, apersonal digital assistant (PDA), a fixed location data unit, and acomputer, into which the memory array is integrated.
 16. An apparatuscomprising: a magnetic tunneling junction device comprising: a freelayer; a tunnel barrier layer adjacent to the free layer; and a spintorque enhancing layer adjacent to the free layer, the spin torqueenhancing layer comprising a nano-oxide layer, wherein the spin torqueenhancing layer is between the free layer and an electrical contact ofthe magnetic tunneling junction device.
 17. The apparatus of claim 16,further comprising a pinned layer adjacent to the tunnel barrier layer.18. The apparatus of claim 16, further comprising a capping layeradjacent to the spin torque enhancing layer.
 19. The apparatus of claim16, wherein the spin torque enhancing layer reduces a critical switchingcurrent density threshold without substantially increasing a resistanceof the magnetic tunneling junction device.
 20. The apparatus of claim16, integrated into at least one semiconductor die.
 21. The apparatus ofclaim 16, further comprising a memory array that includes the magnetictunneling junction device.
 22. The apparatus of claim 21, furthercomprising a device selected from the group consisting of a set top box,a music player, a video player, an entertainment unit, a navigationdevice, a communications device, a personal digital assistant (PDA), afixed location data unit, and a computer, into which the memory array isintegrated.
 23. An apparatus comprising: a magnetic tunnel junctiondevice comprising: means for storing a data value as an orientation of amagnetic moment that is programmable by a spin polarized currentexceeding a threshold current density; tunneling barrier means forproviding conduction electrons to the means for storing by quantummechanical tunneling of the conduction electrons through a barrier; andspin torque enhancing means for reducing a critical switching currentdensity threshold without substantially decreasing a tunnelingmagnetoresistance (TMR) of the magnetic tunnel junction device, whereinthe spin torque enhancing means includes a nano-oxide layer, and whereinthe means for storing is positioned between the tunneling barrier meansand the spin torque enhancing means.
 24. The apparatus of claim 23,wherein the nano-oxide layer includes an oxidation layer of anon-magnetic metal alloy.
 25. The apparatus of claim 23, integrated inat least one semiconductor die.
 26. The apparatus of claim 23, furthercomprising a memory array that includes the magnetic tunnel junctiondevice including the means for storing, the tunneling barrier means, andthe spin torque enhancing means.
 27. The apparatus of claim 26, furthercomprising a device selected from the group consisting of a set top box,a music player, a video player, an entertainment unit, a navigationdevice, a communications device, a personal digital assistant (PDA), afixed location data unit, and a computer, into which the memory array isintegrated.
 28. A method comprising: forming a free layer above a tunnelbarrier layer of a magnetic tunneling junction structure; and forming aspin torque enhancing layer above the free layer, the spin torqueenhancing layer comprising a nano-oxide layer.
 29. The method of claim28, further comprising: forming a tunnel barrier layer adjacent to thefree layer.
 30. The method of claim 29, further comprising: forming apinned layer adjacent to the tunnel barrier layer.
 31. The method ofclaim 28, wherein the nano-oxide layer is formed by oxidizing anon-magnetic metal alloy.
 32. The method of claim 28, further comprisingforming a capping layer above the spin torque enhancing layer.
 33. Themethod of claim 28, wherein forming the free layer and forming the spintorque enhancing layer are controlled by a processor integrated into anelectronic device.
 34. A method comprising: a first step for forming afree layer above a tunnel barrier layer of a magnetic tunneling junctionstructure; and a second step for forming a spin torque enhancing layerabove the free layer, the spin torque enhancing layer comprising anano-oxide layer.
 35. The method of claim 34, further comprising: athird step for forming a pinned layer adjacent to the tunnel barrierlayer; and a fourth step for forming a capping layer above the spintorque enhancing layer.
 36. The method of claim 34, wherein the firststep and the second step are controlled by a processor integrated intoan electronic device.
 37. A computer readable tangible medium storinginstructions executable by a computer, the instructions comprising:instructions that are executable by the computer to initiate formationof a free layer above a tunnel barrier layer of a magnetic tunnelingjunction structure; and instructions that are executable by the computerto initiate formation of a spin torque enhancing layer above the freelayer, the spin torque enhancing layer comprising a nano-oxide layer.38. The computer readable tangible medium of claim 37, the instructionsfurther comprising: instructions that are executable by the computer toinitiate formation of a pinned layer adjacent to the free layer.
 39. Thecomputer readable tangible medium of claim 37, the instructions furthercomprising: instructions that are executable by the computer to initiateformation of a pinning layer adjacent the pinned layer.
 40. A methodcomprising: receiving design information representing at least onephysical property of a semiconductor device, the semiconductor devicecomprising: a free layer; a tunnel barrier layer adjacent to the freelayer; and a spin torque enhancing layer adjacent to the free layer, thespin torque enhancing layer comprising a nano-oxide layer; transformingthe design information to comply with a file format; and generating adata file comprising the transformed design information.
 41. The methodof claim 40, wherein the nano-oxide layer includes an oxidation layer ofa non-magnetic metal alloy.
 42. The method of claim 40, wherein the datafile has a GDSII format.
 43. A method comprising: receiving a data filecomprising design information corresponding to a semiconductor device;and fabricating the semiconductor device according to the designinformation, wherein the semiconductor device includes: a free layer; atunnel barrier layer adjacent to the free layer; and a spin torqueenhancing layer adjacent to the free layer, the spin torque enhancinglayer comprising a nano-oxide layer.
 44. The method of claim 43, whereinthe nano-oxide layer includes an oxidation layer of a non-magnetic metalalloy.
 45. The method of claim 43, wherein the data file has a GDSIIformat.
 46. A method comprising: receiving design information comprisingphysical positioning information of a packaged semiconductor device on acircuit board, the packaged semiconductor device comprising a structurecomprising: a free layer; a tunnel barrier layer adjacent to the freelayer; and a spin torque enhancing layer adjacent to the free layer, thespin torque enhancing layer comprising a nano-oxide layer; andtransforming the design information to generate a data file.
 47. Themethod of claim 46, wherein the nano-oxide layer includes an oxidationlayer of a non-magnetic metal alloy.
 48. The method of claim 46, whereinthe data file has a GERBER format.
 49. A method comprising: receiving adata file comprising design information comprising physical positioninginformation of a packaged semiconductor device on a circuit board; andmanufacturing the circuit board configured to receive the packagedsemiconductor device according to the design information, wherein thepackaged semiconductor device includes a semiconductor memory arraycomprising at least one memory cell that includes: a free layer; atunnel barrier layer adjacent to the free layer; and a spin torqueenhancing layer adjacent to the free layer, the spin torque enhancinglayer comprising a nano-oxide layer.
 50. The method of claim 49, whereinthe nano-oxide layer includes an oxidation layer of a non-magnetic metalalloy.
 51. The method of claim 49, wherein the data file has a GERBERformat.
 52. The method of claim 49, further comprising integrating thecircuit board into a device selected from the group consisting of a settop box, a music player, a video player, an entertainment unit, anavigation device, a communications device, a personal digital assistant(PDA), a fixed location data unit, and a computer.